Exemplary embodiments of the present invention relate to a delay line, and more particularly, to a delay line for a semiconductor device for delaying an input signal.
A synchronous semiconductor device including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) transfers data to external devices using an internal clock, which is synchronized with an external clock inputted from an external device, e.g., a memory controller.
In order to stably transfer data between a memory cell and an external device, time synchronization between and the data outputted from the memory cell and an external clock, which is applied from the external device to the memory cell is important.
The data outputted from the memory cell is synchronized with an internal clock. The internal clock is synchronized with the external clock when the external clock is applied to the memory cell. But, the internal clock is delayed through elements of the memory cell, and thus, the internal clock is not synchronized with the external clock when the data is outputted from the memory cell. That is, the data is not synchronized with the external clock.
Accordingly, in order to stably transfer data between the memory cell and the external device, the internal clock should be synchronized with the external clock by compensating the internal clock for a data bus time so that a delayed internal clock is correctly positioned on an edge or a center of the external clock applied from the external device.
Herein, the internal clock is a delayed clock of an external clock applied from the external device, and the external clock is delayed through a delay circuit, which replicates a delay caused by elements of the memory cell. Because a delay amount of the delay circuit is not variable, a phase of the internal clock is further delayed until the internal clock is synchronized with the external clock.
That is, because a phase difference between the internal clock and the external clock may not be calculated in advance, and may be variable according to an operation condition of the memory cell, the internal clock is delayed through the delay circuit of which a delay amount is varied in response to a control signal in order to correctly synchronize the internal clock with the external clock.
Moreover, in the case of a worst operation condition of the memory cell, when a phase difference between the internal clock and the external clock is one clock cycle 1tck, the internal clock must be delayed through a delay circuit having a large variable delay amount in response to a control signal to synchronize the external clock with the internal clock.
Meanwhile, since the replicated/modeled delay amount (hereinafter, delay amount) of the delay circuit which replicates a delay of the memory is not a variable value, theoretically, the replicated delay amount is different from a real delay amount in a real memory device because circuits may have a variable delay amount (e.g., an input buffer circuit or an output buffer circuit which buffers input/output signals) that depend on Process, Voltage, and Temperature (PVT) variation.
The difference between the replicated delay amount and the real delay amount is caused by the variations of the real delay amount based on the PVT variation. Accordingly, in order to compensate for this difference, a delay line having the modeled delay amount uses elements (e.g., a resistor or a capacitor), insensitive to the PVT variation, even though the real delay amount is determined by an operation of a CMOS transistor having a different characteristic than a resistor or capacitor.
However, if elements having different characteristics are used, because a variation width of an absolute delay amount depending on a level change of a power supply voltage VDD is different for each element, it is difficult to match the modeled/replicated delay amount with the real delay amount by a variation of the absolute delay amount.
That is, as shown in FIG. 1, because a conventional delay circuit performs a variation of a delay amount in response to control signals DCON<0:N>, but does not compensate for the change of the delay amount depending on the change of the power supply voltage VDD, it does not accurately match the replicated delay amount with the real delay amount.
This problem may occur in the conventional semiconductor devices, where the power supply VDD has an operation voltage range from 1.8V to 1.2V.